(Français) Projet Archi-CESAM

Converged, Efficient and Safe Architecture based on Near Memory Accelerators

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Rethink hardware so that it is co-designed with the application, with a view to converged architecture and trust in an environment with abundant data to process

Denis Dutoit, Head of the computing and digital architectures program at CEA-List

Keywords: Digital architecture, rack-scale computing, disaggregated heterogeneous architectures, memory-centric architectures, hardware gas pedals, energy efficiency, design, formal methods

European cloud sovereignty includes control over processors and gas pedals. With Dennard’s Law coming to an end and Moore’s Law slowing down, processor performance will evolve towards more parallelism (multi-core), more specialization (gas pedals), and integrating new interconnections. Virtualization, by separating hardware resources from logical ones, facilitates converged architectures, making the cloud more modular, fast and agile. However, this increased complexity makes the intermediate adaptation layer harder to validate and more prone to failure.

The Archi-CESAM project proposes to rethink hardware (computation, memory and interconnection) so that it is co-designed with the application in a converged and trusted architecture perspective, in an environment known for its abundance of data to be processed. The Archi-CESAM project tackles this major Cloud evolution with a global, coordinated approach to distributed architectures, acceleration, interconnection and security bricks, not forgetting design methods.

— Missions

— Our researches

Hardware architectures for rack-scale computing

Develop a rack-scale architecture simulator offering new, efficient virtualization primitives capable of scaling up to a hundred hardware components, while demonstrating the efficiency and usefulness of this architecture.


Memory-centric architectures

Offering extra-functional building blocks for security and interconnections, which are key components of architectures handling large quantities of data


Hardware Accelerators

Develop hardware function blocks for acceleration with resource virtualization tools, as well as gas pedal programming/synthesis languages and tools.


Design method based on formal methods

By modeling and verifying case studies from other work packages, ensure confidence in these new hardware architectures

Partners

Consortium

Inria, CEA, Université de Rennes, Télécom SudParis, GINP, CNRS

— Research team

9 permanent staff (not funded by the project)
19 people funded by the project, including :
9 PhD students
4 post-docs
6 engineers

Our teams in France


Other projects

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