Converged, Efficient and Safe Architecture based on Near Memory Accelerators
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Rethink hardware so that it is co-designed with the application, with a view to converged architecture and trust in an environment with abundant data to process
Adrian Evans, Research engineer at CEA LIST
Keywords: Digital architecture, rack-scale computing, disaggregated heterogeneous architectures, memory-centric architectures, hardware gas pedals, energy efficiency, design, formal methods
European cloud sovereignty includes control over processors and gas pedals. With Dennard’s Law coming to an end and Moore’s Law slowing down, processor performance will evolve towards more parallelism (multi-core), more specialization (gas pedals), and integrating new interconnections. Virtualization, by separating hardware resources from logical ones, facilitates converged architectures, making the cloud more modular, fast and agile. However, this increased complexity makes the intermediate adaptation layer harder to validate and more prone to failure.
The Archi-CESAM project proposes to rethink hardware (computation, memory and interconnection) so that it is co-designed with the application in a converged and trusted architecture perspective, in an environment known for its abundance of data to be processed. The Archi-CESAM project tackles this major Cloud evolution with a global, coordinated approach to distributed architectures, acceleration, interconnection and security bricks, not forgetting design methods.
— Missions
— Our researches
— Partners
Consortium
Inria, CEA, Université de Rennes, Télécom SudParis, GINP, CNRS
— Research team
9 permanent staff (not funded by the project)
19 people funded by the project, including :
9 PhD students
4 post-docs
6 engineers
Our teams in France
— Publications
Journal articles
- Louka Yerly, Arthur Perais. Privilege Level Dynamics and Their Impact on Conditional Branch Prediction Performance in FaaS. IEEE Computer Architecture Letters, 2026, Early access, pp.1-4. ⟨10.1109/LCA.2026.3703184⟩. ⟨hal-05662957⟩
Conference papers
- Damien Simon, Olivier Sentieys, Sylvain Lefebvre. Hardware Stencil Accelerator with Periodic Boundary Conditions. FCCM 2026 - 34th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, May 2026, Atlanta, United States. pp.213-221, ⟨10.1109/FCCM68464.2026.00039⟩. ⟨hal-05665519⟩
- Philippe Ledent, Radu Mateescu, Wendelin Serwe. Improving PSS Test Generation Using Model Checking and Conformance Testing. FDL 2024 - 27th Forum on specification and Design Languages, Sep 2024, Stockholm, Sweden. pp.1-9, ⟨10.1109/FDL63219.2024.10673842⟩. ⟨hal-04719995⟩
- Rémi Dulong, Nathan Felber, Pascal Felber, Gilles Hopin, Baptiste Lepers, et al.. P 4 ce: consensus over RDMA at line speed. ICDCS 2024 - IEEE 44th International Conference on Distributed Computing Systems, Jul 2024, Jersey City, United States. pp.508-519, ⟨10.1109/ICDCS60910.2024.00054⟩. ⟨hal-04895326⟩
Poster communications
- Zachary Assoumani, César Fuguet, Radu Mateescu, Wendelin Serwe. On Benefits of Modeling the HPDcache in LNT. RISC-V 2025 -RISC-V Summit Europe, May 2025, Paris, France. pp.1-1, 2025. ⟨hal-05106202⟩
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